Introduced on Sept 30, 1996 by Fujitsu, the TurboSPARC CPU (aka the MB86907) was designed to "double" the performance of SPARCstation 5 and compatible workstations.
At the time, Fujitsu's TurboSPARC processor was the most powerful of the highly-integrated, low-end SPARC microprocessors now available. Performance meets or exceeds 143 SPECint/92 and 119 SPECfp92. In comparison, typical performance ratings for workstations based on microSPARC-II CPUs at 110 MHz were 78 SPEC/int92 and 65 SPEC/fp92.
The TurboSPARC was built with a nine-stage pipeline and 16 KB of instruction cache and 16 KB data cache, with support for up to 1MB of secondary cache. The device's streaming cache architecture minimizes delays caused by cache misses. It is a SPARC version 8 compliant chip. TurboSPARC is also 'energy-efficient,' with typical power dissipation of just seven watts.
The Fujitsu TurboSPARC Microprocessor is a high frequency, highly integrated single-chip CPU providing balanced integer and floating point performance. The TurboSPARC microprocessor is an implementation of the SPARC V.8 architecture and is ideally suited for low-cost uniprocessor applications.
The TurboSPARC microprocessor derives its high performance from a number of design techniques. A 170 MHz operating frequency, large 16 KByte instruction and 16 KByte data caches utilizing a streaming architecture which helps to minimize cache miss delays, numerous dedicated address translation caches, on-chip secondary cache and DRAM control interfaces, along with an efficient 9-stage pipeline, all combine to offer a device whose performance is at the cutting-edge of today's microprocessor technology.
The TurboSPARC microprocessor contains an Integer Unit (IU), Floating Point Controller (FPC), Floating Point ALU, Multiply, and Divide/Square? Root Units, Instruction and Data caches, Memory Management Unit (MMU), and Secondary cache, DRAM, SBus, and AFX bus controllers. The various on-chip controllers help to increase performance while simplifying system design.
Figure 1. TurboSPARC CPU Block Diagram
* SPARC V.8 32-bit High Performance RISC Architecture * 170 MHz Operating Frequency * 143 SPECint92 - 119 SPECfp92 * 16 KByte Direct Mapped Instruction Cache * 16 KByte Direct Mapped Data Cache * 8-Window, 136-word Register File * Supports up to 1 MByte of Secondary Cache * On-chip Memory Management Unit * Programmable On-chip memory controllers * Programmable System Clock Frequencies * 0.35 micron CMOS Technology * Compatible with microSPARC-II * Compatible with SunOS? and Solaris * Compatible with Current Software Applications * IEEE 1149.1 Boundary Scan Test Interface * Low-Cost 416 PBGA Package * 7 W Typical Power Dissipation
* The cache controller supplies all necessary secondary cache signals including a dedicated address bus and is capable of supporting up to 1 MByte of secondary cache. * The DRAM controller contains all necessary signals for interfacing to industry standard page-mode DRAMs. * The SBus controller handles the interface between the processor and other bus masters, and provides all of the signals as defined in the Sun Microsystems SBus Specification. * The AFX graphics bus controller supplies all necessary signals for interfacing to the Sun Microsystems compati-ble AFX graphics bus.
Figure 2. TurboSPARC Processor With 512 KByte Secondary Cache Configuration
The TurboSPARC Processor came out very close to the end of the sparc32 period. Despite being faster than all other sparc32 processors, the TurboSPARC saw very limited deployment. The only two systems known to have incorporated the TurboSPARC are the Tadpole 3TX and a SPARCStation 5 variant (Sun didn't ship any SPARCStation 5s with a TurboSPARC, but it was a common after-market upgrade).
The technical documentation from Fujitsu for the TurboSPARC MB86907 is known to be incorrect in several places.
Linux, while able to boot and detect the TurboSPARC CPU, has mediocre support for the processor at best.